The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. Riahi, P. A., Navabi, Z., & Lombardi, F. In Asian Test Symposium, pages 274-277, 2003. IEEE Computer Society.
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. [link]Link  The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. [link]Paper  bibtex   
@inproceedings{conf/ats/RiahiNL03,
  added-at = {2016-01-13T00:00:00.000+0100},
  author = {Riahi, Pedram A. and Navabi, Zainalabedin and Lombardi, Fabrizio},
  biburl = {http://www.bibsonomy.org/bibtex/2ded78e4d2b87f24f4a1e191624a0b231/dblp},
  booktitle = {Asian Test Symposium},
  crossref = {conf/ats/2003},
  ee = {http://doi.ieeecomputersociety.org/10.1109/ATS.2003.1250822},
  interhash = {7c7a8d7399f489356b9f22428905a7c4},
  intrahash = {ded78e4d2b87f24f4a1e191624a0b231},
  isbn = {0-7695-1951-2},
  keywords = {dblp},
  pages = {274-277},
  publisher = {IEEE Computer Society},
  timestamp = {2016-01-15T11:37:06.000+0100},
  title = {The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.},
  url = {http://dblp.uni-trier.de/db/conf/ats/ats2003.html#RiahiNL03},
  year = 2003
}
Downloads: 0