Design and implementation of the discrete wavelet transform on an FPGA platform to process data sets of up to three dimensions. Rivera-Juarico, E., A., Ramirez-Cortes, J., M., Alarcon-Aquino, V., & Escamilla-Ambrosio, J. In CONIELECOMP 2012, 22nd International Conference on Electrical Communications and Computers, pages 333-338, 2, 2012. IEEE.
Design and implementation of the discrete wavelet transform on an FPGA platform to process data sets of up to three dimensions [link]Website  doi  abstract   bibtex   
The aim of this work is the design and implementation of a DWT architecture FPGA-based platform for up to three dimensional signal processing. First, filter banks are designed using a distributed arithmetic technique. Then, we design controllers, interfaces and protocols that handle, transmit and sequence all the data during the computing process. Data is sent via USB to the FPGA and the user interface is programmed in MATLAB. A graphical user interface manages the system operation and displays the results on a PC. Designed filters are compared with a fully parallel architecture in relation to the number of gates used, speed, and algorithm performance. © 2012 IEEE.
@inproceedings{
 title = {Design and implementation of the discrete wavelet transform on an FPGA platform to process data sets of up to three dimensions},
 type = {inproceedings},
 year = {2012},
 keywords = {Daubechies,Distributed Arithmetic,Filter Design},
 pages = {333-338},
 websites = {http://ieeexplore.ieee.org/document/6189934/},
 month = {2},
 publisher = {IEEE},
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 abstract = {The aim of this work is the design and implementation of a DWT architecture FPGA-based platform for up to three dimensional signal processing. First, filter banks are designed using a distributed arithmetic technique. Then, we design controllers, interfaces and protocols that handle, transmit and sequence all the data during the computing process. Data is sent via USB to the FPGA and the user interface is programmed in MATLAB. A graphical user interface manages the system operation and displays the results on a PC. Designed filters are compared with a fully parallel architecture in relation to the number of gates used, speed, and algorithm performance. © 2012 IEEE.},
 bibtype = {inproceedings},
 author = {Rivera-Juarico, E. A. and Ramirez-Cortes, J. M. and Alarcon-Aquino, V. and Escamilla-Ambrosio, J.},
 doi = {10.1109/CONIELECOMP.2012.6189934},
 booktitle = {CONIELECOMP 2012, 22nd International Conference on Electrical Communications and Computers}
}

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