@inProceedings{
 title = {An IIP2 digital calibration technique for passive CMOS down-converters},
 type = {inProceedings},
 year = {2010},
 identifiers = {[object Object]},
 id = {d67e6a96-9668-3bd6-b1ca-9c8c7da5f82f},
 created = {2017-12-04T05:34:39.230Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:34:39.230Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {The IIP2 requirement in fully integrated direct-conversion receivers using FDD duplexing is prohibitively high and demands the use of an external filter in order to attenuate the leakage from the transmitter. This paper presents a digital calibration technique for passive CMOS down-converters that allows a direct conversion receiver achieve the requirements without external filtering. A Least-Mean-Square optimization algorithm is used in order to reduce the low-frequency second-order intermodulation product. The algorithm controls the digital calibration structures at the biasing of the passive mixer and adapts them until the second order intermodulation drops below the noise level. The method is tested by calibrating a 1.2-V 65nm CMOS passive mixer targeting UMTS/LTE applications at several corner conditions including worst case mismatches in the switching pairs. ©2010 IEEE.},
 bibtype = {inProceedings},
 author = {Rodriguez, S. and Tao, S. and Ismail, M. and Rusu, A.},
 booktitle = {ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems}
}

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