@article{
 title = {A triple-mode sigma-delta modulator for multi-standard wireless radio receivers},
 type = {article},
 year = {2006},
 identifiers = {[object Object]},
 keywords = {Analog-to-digital conversion,Feedforward path,Multi-standard,Sigma-delta modulator,Triple-mode,Wireless radio receiver},
 volume = {47},
 id = {a23701b5-a685-31be-b00a-02ba8635d468},
 created = {2017-12-04T05:34:42.467Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:34:42.467Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {A l .8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted- Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2  MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN. © 2006 Springer Science + Business Media, Inc.},
 bibtype = {article},
 author = {Rusu, A. and Borodenkov, A. and Ismail, M. and Tenhunen, H.},
 journal = {Analog Integrated Circuits and Signal Processing},
 number = {2}
}

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