@inproceedings{4267429,
	Author = {Sadowski, R.W. and Ballmann, M.C. and Shoop, B.L.},
	Booktitle = {Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on},
	Date-Added = {2012-08-20 12:52:39 +0000},
	Date-Modified = {2012-08-28 18:16:07 +0000},
	Doi = {10.1109/MWSCAS.2006.381805},
	Issn = {1548-3746},
	Keywords = {bias voltages;digital halftoning;flip-chip bonded photodiode array;hardware approach;image processing;modified current starved comparator;neural network CMOS circuit implementation;optoelectronic devices;quantizing element;real-time halftoning applications;CMOS digital integrated circuits;flip-chip devices;image processing;integrated circuit design;neural nets;optoelectronic devices;photodiodes;},
	Month = {8},
	Pages = {614 -618},
	Title = {A Neural Network CMOS Circuit Implementation for Real-Time Halftoning Applications},
	Volume = {2},
	Year = {2006},
	Abstract = {We report on an underlying hardware approach to implement a neural network for real-time image halftoning. We present simulation and experimental results using a modified current starved comparator as the quantizing element that has a 40 fold reduction in pixel current over our previous designs. The neuron is self-biasing with error weighting achieved through current division to enable operation at a variety of bias voltages. The circuit is designed for integration with a flip-chip bonded photodiode array for imaging applications.},
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	Bdsk-Url-1 = {http://dx.doi.org/10.1109/MWSCAS.2006.381805}}

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