A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing. Sadredini, E., Rahimi, R., Verma, V., Stan, M. R., & Skadron, K. IEEE computer architecture letters, 2019.
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Paper bibtex
Paper bibtex @article{2622,
author = {Elaheh Sadredini and Reza Rahimi and Vishal Verma and Mircea R. Stan and Kevin Skadron},
title = {A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing},
year = {2019},
journal = {IEEE computer architecture letters},
url = {https://doi.org/10.1109/lca.2019.2909870}
}Downloads: 0
{"_id":"SAD5e928J56wdqEau","bibbaseid":"sadredini-rahimi-verma-stan-skadron-ascalableandefficientinmemoryinterconnectarchitectureforautomataprocessing-2019","author_short":["Sadredini, E.","Rahimi, R.","Verma, V.","Stan, M. R.","Skadron, K."],"bibdata":{"bibtype":"article","type":"article","author":[{"firstnames":["Elaheh"],"propositions":[],"lastnames":["Sadredini"],"suffixes":[]},{"firstnames":["Reza"],"propositions":[],"lastnames":["Rahimi"],"suffixes":[]},{"firstnames":["Vishal"],"propositions":[],"lastnames":["Verma"],"suffixes":[]},{"firstnames":["Mircea","R."],"propositions":[],"lastnames":["Stan"],"suffixes":[]},{"firstnames":["Kevin"],"propositions":[],"lastnames":["Skadron"],"suffixes":[]}],"title":"A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing","year":"2019","journal":"IEEE computer architecture letters","url":"https://doi.org/10.1109/lca.2019.2909870","bibtex":"@article{2622,\n author = {Elaheh Sadredini and Reza Rahimi and Vishal Verma and Mircea R. Stan and Kevin Skadron},\n title = {A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing},\n year = {2019},\n journal = {IEEE computer architecture letters},\n url = {https://doi.org/10.1109/lca.2019.2909870}\n}\n\n","author_short":["Sadredini, E.","Rahimi, R.","Verma, V.","Stan, M. R.","Skadron, K."],"key":"2622","id":"2622","bibbaseid":"sadredini-rahimi-verma-stan-skadron-ascalableandefficientinmemoryinterconnectarchitectureforautomataprocessing-2019","role":"author","urls":{"Paper":"https://doi.org/10.1109/lca.2019.2909870"},"metadata":{"authorlinks":{}}},"bibtype":"article","biburl":"https://bibbase.org/f/fFERMKNwKyHLsDPJ3/Link_Lab_Publications.bib","dataSources":["GXL8BuKffZ6XGRvhu","zTwdZBrCqogZ6yMmD","A9Zuq8B85Rd3bHeNs","zq8E4CA9zBjkA2p7P","b7zvHnuSqhTvwNoon","BE493TFz6wWiE9NkC","6CYcgzsh5rhZhtcXe","DesgNCELw9F4LSokr","WCSuxR2upo4FXxxRm","JSGNr3KwokFPgXiz5","RbCkvcfqfbgtxTyNT","mwAui9iKniQyhTc49"],"keywords":[],"search_terms":["scalable","efficient","memory","interconnect","architecture","automata","processing","sadredini","rahimi","verma","stan","skadron"],"title":"A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing","year":2019}