{"_id":"T7YwuBKEyDeJNPMw7","bibbaseid":"sahula-ravikumar-improvingvlsidesignprocessesusinghierarchicalconcurrentflowgraphapproach-2000","author_short":["Sahula, V","Ravikumar, C P"],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","title":"Improving VLSI design processes using Hierarchical concurrent flow graph approach","author":[{"propositions":[],"lastnames":["Sahula"],"firstnames":["V"],"suffixes":[]},{"propositions":[],"lastnames":["Ravikumar"],"firstnames":["C","P"],"suffixes":[]}],"booktitle":"4th IEEE VLSI Design and Test Workshops","year":"2000","bibtex":"@InProceedings{ravikumar2000improving,\r\n Title = {{Improving VLSI design processes using Hierarchical concurrent flow graph approach}},\r\n Author = {Sahula, V and Ravikumar, C P},\r\n Booktitle = {4th IEEE VLSI Design and Test Workshops},\r\n Year = {2000}\r\n}\r\n\r\n","author_short":["Sahula, V","Ravikumar, C P"],"key":"ravikumar2000improving","id":"ravikumar2000improving","bibbaseid":"sahula-ravikumar-improvingvlsidesignprocessesusinghierarchicalconcurrentflowgraphapproach-2000","role":"author","urls":{},"metadata":{"authorlinks":{}}},"bibtype":"inproceedings","biburl":"https://bibbase.org/network/files/xKC5GQKZ8FRtFCvB4","dataSources":["FzvqmGdTCZ7Dbyn6A","ya2CyA73rpZseyrZ8","2252seNhipfTmjEBQ","JSHXsrzTtzwdTXGqc"],"keywords":[],"search_terms":["improving","vlsi","design","processes","using","hierarchical","concurrent","flow","graph","approach","sahula","ravikumar"],"title":"Improving VLSI design processes using Hierarchical concurrent flow graph approach","year":2000}