Improvement of ASIC design processes. Sahula, V., Ravikumar, C., P., & Nagchoudhuri, D. In Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, pages 105-110, 2002. IEEE Comput. Soc.
![Improvement of ASIC design processes [pdf]](https://bibbase.org/img/filetypes/pdf.svg "pdf")
Paper ![Improvement of ASIC design processes [link]](https://bibbase.org/img/filetypes/link.svg "link")
Website doi abstract bibtex
Paper Website doi abstract bibtex With device counts on modem-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow that will be followed for project execution. The second problem is that of making incremental changes to the design flow in order to reduce the time to complete a project. We consider these two problems in a theoretical framework. Starting from a textual description of the design flow, a model known as the hierarchical concurrent flow graph (HCFG) model is constructed to capture the concurrency in the execution of an ASIC design flow and the inherent hierarchy in such a flow. The HCFG model allows us to (a) quickly estimate the project execution time and (b) analyze the effect of introducing AND and OR concurrency in the flow to improve the execution time. We illustrate the use of the powerful estimation technique through two examples. The first example shows the use of AND concurrency in a back-end flow and the second example shows the use of OR concurrency in a software design flow
@inproceedings{
title = {Improvement of ASIC design processes},
type = {inproceedings},
year = {2002},
keywords = {AND concurrency,ASIC design processes,Application specific integrated circuits,Asia,Concurrent computing,Educational institutions,Flow graphs,Instruments,Meeting planning,OR concurrency,Power system modeling,Process design,Project management,application specific integrated circuits,circuit CAD,circuit layout CAD,design flow,flow graphs,hierarchical concurrent flow graph model,high level synthesis,incremental changes,integrated circuit design,project execution time,textual description},
pages = {105-110},
websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=994893},
publisher = {IEEE Comput. Soc},
id = {2396f592-b65b-3d06-a688-63110100c1f8},
created = {2016-05-10T02:54:42.000Z},
accessed = {2015-12-15},
file_attached = {true},
profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
last_modified = {2017-03-14T01:22:09.162Z},
read = {false},
starred = {false},
authored = {true},
confirmed = {true},
hidden = {false},
citation_key = {Sahula2002},
short_title = {Design Automation Conference, 2002. Proceedings of},
private_publication = {false},
abstract = {With device counts on modem-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow that will be followed for project execution. The second problem is that of making incremental changes to the design flow in order to reduce the time to complete a project. We consider these two problems in a theoretical framework. Starting from a textual description of the design flow, a model known as the hierarchical concurrent flow graph (HCFG) model is constructed to capture the concurrency in the execution of an ASIC design flow and the inherent hierarchy in such a flow. The HCFG model allows us to (a) quickly estimate the project execution time and (b) analyze the effect of introducing AND and OR concurrency in the flow to improve the execution time. We illustrate the use of the powerful estimation technique through two examples. The first example shows the use of AND concurrency in a back-end flow and the second example shows the use of OR concurrency in a software design flow},
bibtype = {inproceedings},
author = {Sahula, V. and Ravikumar, C. P. and Nagchoudhuri, D.},
doi = {10.1109/ASPDAC.2002.994893},
booktitle = {Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design}
}Downloads: 0
{"_id":"LyqzNMrgvimxrspvK","bibbaseid":"sahula-ravikumar-nagchoudhuri-improvementofasicdesignprocesses-2002","author_short":["Sahula, V.","Ravikumar, C., P.","Nagchoudhuri, D."],"bibdata":{"title":"Improvement of ASIC design processes","type":"inproceedings","year":"2002","keywords":"AND concurrency,ASIC design processes,Application specific integrated circuits,Asia,Concurrent computing,Educational institutions,Flow graphs,Instruments,Meeting planning,OR concurrency,Power system modeling,Process design,Project management,application specific integrated circuits,circuit CAD,circuit layout CAD,design flow,flow graphs,hierarchical concurrent flow graph model,high level synthesis,incremental changes,integrated circuit design,project execution time,textual description","pages":"105-110","websites":"http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=994893","publisher":"IEEE Comput. Soc","id":"2396f592-b65b-3d06-a688-63110100c1f8","created":"2016-05-10T02:54:42.000Z","accessed":"2015-12-15","file_attached":"true","profile_id":"03d2ca17-6bde-3cfe-95de-fcbe4f21507b","last_modified":"2017-03-14T01:22:09.162Z","read":false,"starred":false,"authored":"true","confirmed":"true","hidden":false,"citation_key":"Sahula2002","short_title":"Design Automation Conference, 2002. Proceedings of","private_publication":false,"abstract":"With device counts on modem-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow that will be followed for project execution. The second problem is that of making incremental changes to the design flow in order to reduce the time to complete a project. We consider these two problems in a theoretical framework. Starting from a textual description of the design flow, a model known as the hierarchical concurrent flow graph (HCFG) model is constructed to capture the concurrency in the execution of an ASIC design flow and the inherent hierarchy in such a flow. The HCFG model allows us to (a) quickly estimate the project execution time and (b) analyze the effect of introducing AND and OR concurrency in the flow to improve the execution time. We illustrate the use of the powerful estimation technique through two examples. The first example shows the use of AND concurrency in a back-end flow and the second example shows the use of OR concurrency in a software design flow","bibtype":"inproceedings","author":"Sahula, V. and Ravikumar, C. P. and Nagchoudhuri, D.","doi":"10.1109/ASPDAC.2002.994893","booktitle":"Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design","bibtex":"@inproceedings{\n title = {Improvement of ASIC design processes},\n type = {inproceedings},\n year = {2002},\n keywords = {AND concurrency,ASIC design processes,Application specific integrated circuits,Asia,Concurrent computing,Educational institutions,Flow graphs,Instruments,Meeting planning,OR concurrency,Power system modeling,Process design,Project management,application specific integrated circuits,circuit CAD,circuit layout CAD,design flow,flow graphs,hierarchical concurrent flow graph model,high level synthesis,incremental changes,integrated circuit design,project execution time,textual description},\n pages = {105-110},\n websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=994893},\n publisher = {IEEE Comput. Soc},\n id = {2396f592-b65b-3d06-a688-63110100c1f8},\n created = {2016-05-10T02:54:42.000Z},\n accessed = {2015-12-15},\n file_attached = {true},\n profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},\n last_modified = {2017-03-14T01:22:09.162Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {true},\n hidden = {false},\n citation_key = {Sahula2002},\n short_title = {Design Automation Conference, 2002. Proceedings of},\n private_publication = {false},\n abstract = {With device counts on modem-day ASICs crossing the 10 million mark, careful planning of an ASIC design project is necessary to meet time deadlines. Two problems arise in this context. The first is the estimation of man-months for a project, with the knowledge of the ASIC design flow that will be followed for project execution. The second problem is that of making incremental changes to the design flow in order to reduce the time to complete a project. We consider these two problems in a theoretical framework. Starting from a textual description of the design flow, a model known as the hierarchical concurrent flow graph (HCFG) model is constructed to capture the concurrency in the execution of an ASIC design flow and the inherent hierarchy in such a flow. The HCFG model allows us to (a) quickly estimate the project execution time and (b) analyze the effect of introducing AND and OR concurrency in the flow to improve the execution time. We illustrate the use of the powerful estimation technique through two examples. The first example shows the use of AND concurrency in a back-end flow and the second example shows the use of OR concurrency in a software design flow},\n bibtype = {inproceedings},\n author = {Sahula, V. and Ravikumar, C. P. and Nagchoudhuri, D.},\n doi = {10.1109/ASPDAC.2002.994893},\n booktitle = {Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design}\n}","author_short":["Sahula, V.","Ravikumar, C., P.","Nagchoudhuri, D."],"urls":{"Paper":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b/file/4aaf56e7-46ea-bfa9-1eec-073e3d1636c1/2002-Improvement_of_ASIC_design_processes.pdf.pdf","Website":"http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=994893"},"biburl":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b","bibbaseid":"sahula-ravikumar-nagchoudhuri-improvementofasicdesignprocesses-2002","role":"author","keyword":["AND concurrency","ASIC design processes","Application specific integrated circuits","Asia","Concurrent computing","Educational institutions","Flow graphs","Instruments","Meeting planning","OR concurrency","Power system modeling","Process design","Project management","application specific integrated circuits","circuit CAD","circuit layout CAD","design flow","flow graphs","hierarchical concurrent flow graph model","high level synthesis","incremental changes","integrated circuit design","project execution time","textual description"],"metadata":{"authorlinks":{}}},"bibtype":"inproceedings","biburl":"https://bibbase.org/service/mendeley/03d2ca17-6bde-3cfe-95de-fcbe4f21507b","dataSources":["foRZzjCMmTPmTF8eH","ya2CyA73rpZseyrZ8"],"keywords":["and concurrency","asic design processes","application specific integrated circuits","asia","concurrent computing","educational institutions","flow graphs","instruments","meeting planning","or concurrency","power system modeling","process design","project management","application specific integrated circuits","circuit cad","circuit layout cad","design flow","flow graphs","hierarchical concurrent flow graph model","high level synthesis","incremental changes","integrated circuit design","project execution time","textual description"],"search_terms":["improvement","asic","design","processes","sahula","ravikumar","nagchoudhuri"],"title":"Improvement of ASIC design processes","year":2002}