The hierarchical concurrent flow graph approach for modeling and analysis of design processes

The hierarchical concurrent flow graph approach for modeling and analysis of design processes. Sahula, V. & Ravikumar, C. In Fourteenth IEEE International Conference on VLSI Design, pages 91-96, 2001. IEEE Comput. Soc.

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In this paper, we expose a new technique for the analysis of\ndesign flows. The modern-day chip design process is a complex one, with\nthe following characteristics: (a) the execution times of individual\ntasks are difficult to predict, since a tool may occasionally produce\nunsatisfactory results, requiring the designer to repeat the task, (b)\nthe increasing pressure on the project management to cut down the\ntime-to-market forces the management to employ concurrent design\ntechniques, and (c) the VLSI design flow is hierarchical, and a\ncompletely flat representation of the design flow is too complex to\nanalyze. Existing techniques for design flow analysis cannot deal with\nthe problems mentioned above. The hierarchical concurrent flow graph\n(HCFG) presented in this paper is an analysis technique which borrows\nthe idea of graph transmittance from circuit theory and extends the\nconcept to include hierarchy, concurrency and stochastic variation in\ntask execution times. We apply the HCFG technique to analyze two\nrealistic design flows. We show that a project manager can carry out a\npre-execution “what-if” analysis to determine the best\ndesign flow management strategy, that is most likely to lead to the\nlowest execution time

@inproceedings{
 title = {The hierarchical concurrent flow graph approach for modeling and analysis of design processes},
 type = {inproceedings},
 year = {2001},
 keywords = {Chip scale packaging,Concurrent computing,Design engineering,Educational institutions,Flow graphs,Process design,Project management,Stochastic processes,Time to market,VLSI,Very large scale integration,chip design process,concurrent engineering,design flow management strategy,design processes,execution times,flow graphs,graph transmittance,hierarchical concurrent flow graph approach,integrated circuit design,project management,stochastic variation,task execution times,time-to-market,vlsi,what-if analysis},
 pages = {91-96},
 websites = {http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=902645},
 publisher = {IEEE Comput. Soc},
 id = {3a188958-882d-30ee-8ed0-cdcbc423ee97},
 created = {2016-05-10T02:54:42.000Z},
 accessed = {2015-12-15},
 file_attached = {false},
 profile_id = {03d2ca17-6bde-3cfe-95de-fcbe4f21507b},
 last_modified = {2018-08-05T03:34:07.182Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {true},
 hidden = {false},
 citation_key = {Sahula2001},
 source_type = {inproceedings},
 short_title = {VLSI Design, 2001. Fourteenth International Confer},
 notes = {<b>From Duplicate 2 (<i>The hierarchical concurrent flow graph approach for modeling and analysis of design processes</i> - Sahula, V.; Ravikumar, C.P. P)<br/></b><br/><b>From Duplicate 2 ( </b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/></b><br/><b><br/><i>The hierarchical concurrent flow graph approach for modeling and analysis of design processes</i><br/></b><br/><b><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b>- Sahula, V.; Ravikumar, C.P. P )<br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b>From Duplicate 1 ( </b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/></b><br/><b><br/><i>The hierarchical concurrent flow graph approach for modeling andanalysis of design processes</i><br/></b><br/><b><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b>- Sahula, V.; Ravikumar, C.P. )<br/>And Duplicate 3 ( </b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/></b><br/><b><br/><i>The hierarchical concurrent flow graph approach for modeling andanalysis of design processes</i><br/></b><br/><b><br/><br/><br/></b><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><b>- Sahula, V.; Ravikumar, C.P. )<br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/><br/></b>},
 private_publication = {false},
 abstract = {In this paper, we expose a new technique for the analysis of\ndesign flows. The modern-day chip design process is a complex one, with\nthe following characteristics: (a) the execution times of individual\ntasks are difficult to predict, since a tool may occasionally produce\nunsatisfactory results, requiring the designer to repeat the task, (b)\nthe increasing pressure on the project management to cut down the\ntime-to-market forces the management to employ concurrent design\ntechniques, and (c) the VLSI design flow is hierarchical, and a\ncompletely flat representation of the design flow is too complex to\nanalyze. Existing techniques for design flow analysis cannot deal with\nthe problems mentioned above. The hierarchical concurrent flow graph\n(HCFG) presented in this paper is an analysis technique which borrows\nthe idea of graph transmittance from circuit theory and extends the\nconcept to include hierarchy, concurrency and stochastic variation in\ntask execution times. We apply the HCFG technique to analyze two\nrealistic design flows. We show that a project manager can carry out a\npre-execution &amp;ldquo;what-if&amp;rdquo; analysis to determine the best\ndesign flow management strategy, that is most likely to lead to the\nlowest execution time},
 bibtype = {inproceedings},
 author = {Sahula, V. and Ravikumar, C.P.},
 doi = {10.1109/ICVD.2001.902645},
 booktitle = {Fourteenth IEEE International Conference on VLSI Design}
}

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