CMOS square-law programmable floating resistor. Sakurai, S. & Ismail, M. In Proceedings - IEEE International Symposium on Circuits and Systems, volume 2, 1993.
abstract   bibtex   
A CMOS architecture for a floating linear resistor which exploits the square-law model of the MOS transistor is presented. The architecture is programmable by DC control voltage and it is threshold voltage independent. The architecture is fabricated in a 2μm p-well CMOS MOSIS process. The resistor occupies 210μm × 270μm, consumes 4-4mW with ±V supply and exhibits a sign (at 1% THD) to noise ratio of more than 100dB over a IV range of the DC control voltage.
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 title = {CMOS square-law programmable floating resistor},
 type = {inProceedings},
 year = {1993},
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 volume = {2},
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 abstract = {A CMOS architecture for a floating linear resistor which exploits the square-law model of the MOS transistor is presented. The architecture is programmable by DC control voltage and it is threshold voltage independent. The architecture is fabricated in a 2μm p-well CMOS MOSIS process. The resistor occupies 210μm × 270μm, consumes 4-4mW with ±V supply and exhibits a sign (at 1% THD) to noise ratio of more than 100dB over a IV range of the DC control voltage.},
 bibtype = {inProceedings},
 author = {Sakurai, Satoshi and Ismail, Mohammed},
 booktitle = {Proceedings - IEEE International Symposium on Circuits and Systems}
}

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