Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications. Sassatelli, G., Torres, L., Benoit, P., Gil, T., Diou, C., Cambon, G., & Galy, J. In 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pages 553–558, 2002. IEEE Computer Society.
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/date/SassatelliTBGDCG02,
  author    = {Gilles Sassatelli and
               Lionel Torres and
               Pascal Benoit and
               Thierry Gil and
               Camille Diou and
               Gaston Cambon and
               J{\'{e}}r{\^{o}}me Galy},
  title     = {Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture
               for {DSP} Applications},
  booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
               {(DATE} 2002), 4-8 March 2002, Paris, France},
  pages     = {553--558},
  publisher = {{IEEE} Computer Society},
  year      = {2002},
  url       = {https://doi.org/10.1109/DATE.2002.998355},
  doi       = {10.1109/DATE.2002.998355},
  timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
  biburl    = {https://dblp.org/rec/conf/date/SassatelliTBGDCG02.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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