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This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential clock delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45% resulting in 5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying 1.84 μm2achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70°C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55-0.75 V, and 25°C-110°C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid clock routing measured from 49.5% hamming distance between array's evaluation and wake-up states.

@article{satpathy_4-fj/b_2017, title = {A 4-{fJ}/b {Delay}-{Hardened} {Physically} {Unclonable} {Function} {Circuit} {With} {Selective} {Bit} {Destabilization} in 14-nm {Trigate} {CMOS}}, volume = {52}, issn = {0018-9200}, doi = {10.1109/JSSC.2016.2636859}, abstract = {This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array, fabricated in 14-nm trigate high-k/metal-gate CMOS. Delay-hardened hybrid PUF cells use differential clock delay insertion to favor circuit evaluation in the desired direction while leveraging burn-in-induced aging for selective bit destabilization enabling quick identification and masking of unstable cells, and subsequent temporal-majority-voting with soft dark-bit masking to reduce PUF bit error by 3.9 times to 1.45\% resulting in 5 ppb failure probability. A stable full-entropy 128-b key is finally generated from the 1024 raw PUF bits using BCH error correction and AES-CBC-based entropy extraction. An all-digital design with compact PUF cell layout occupying 1.84 μm2achieves: 1) 4-fJ/b energy-efficiency with 3-μW leakage at 0.65 V, 70°C; 2) peak operating frequency of 1 GHz resulting in 1.2-μs key generation latency; 3) robust operation with stable key generation across 0.55-0.75 V, and 25°C-110°C; 4) 14 times separation between intra/inter-PUF hamming distances with 0.99993 entropy ensuring cryptographic quality randomness and uniqueness; 5) 48\% higher PUF stability with long-term aging by leveraging transistor degradation to reinforce favorable cell bias; and 6) resiliency to power cycling attacks with common centroid clock routing measured from 49.5\% hamming distance between array's evaluation and wake-up states.}, number = {4}, journal = {IEEE Journal of Solid-State Circuits}, author = {Satpathy, S. and Mathew, S. K. and Suresh, V. and Anders, M. A. and Kaul, H. and Agarwal, A. and Hsu, S. K. and Chen, G. and Krishnamurthy, R. K. and De, V. K.}, month = apr, year = {2017}, pages = {940--949} }

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