A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware. Schwarz, M.; Hosticka, B. J.; Kesper, M.; Richert, P.; and Scholles, M. In ASAP, pages 381-391, 1994. IEEE.
A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware. [link]Link  A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware. [link]Paper  bibtex   
@inproceedings{conf/asap/SchwarzHKRS94,
  added-at = {2016-01-20T00:00:00.000+0100},
  author = {Schwarz, Markus and Hosticka, Bedrich J. and Kesper, M. and Richert, Peter and Scholles, Michael},
  biburl = {http://www.bibsonomy.org/bibtex/2a9eabd0c7b93be339281ac9a05a06b17/dblp},
  booktitle = {ASAP},
  crossref = {conf/asap/1994},
  ee = {http://dx.doi.org/10.1109/ASAP.1994.331787},
  interhash = {19a2e65cd0fc6d268db9ad677a709f8b},
  intrahash = {a9eabd0c7b93be339281ac9a05a06b17},
  isbn = {0-8186-6517-3},
  keywords = {dblp},
  pages = {381-391},
  publisher = {IEEE},
  timestamp = {2016-01-21T11:39:34.000+0100},
  title = {A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware.},
  url = {http://dblp.uni-trier.de/db/conf/asap/asap1994.html#SchwarzHKRS94},
  year = 1994
}
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