Low-cost security aware HLS methodology. Sengupta, A., Bhadauria, S., & Mohanty, S. P. IET Computers Digital Techniques, 11(2):68–79, 2017. doi abstract bibtex Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a low-cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4%) through the proposed approach compared with a recent approach.
@article{sengupta_low-cost_2017,
title = {Low-cost security aware {HLS} methodology},
volume = {11},
issn = {1751-8601},
doi = {10.1049/iet-cdt.2016.0014},
abstract = {Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a low-cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4\%) through the proposed approach compared with a recent approach.},
number = {2},
journal = {IET Computers Digital Techniques},
author = {Sengupta, A. and Bhadauria, S. and Mohanty, S. P.},
year = {2017},
keywords = {IC, IP cores, Trojan secured high-level synthesis methodology, candidate datapath resource configuration, design process globalisation, design space, digital integrated circuits, encoding, hardware threats, high level synthesis, industrial property, integrated circuit design, intellectual property cores, invasive software, low-cost Trojan secured schedule, low-cost optimised dual modular redundant design, low-cost security aware HLS methodology, low-cost security-aware HLS approach, resource allocation, scheduling, third party vendors, user constraints, vendor allocation information, vendor allocation procedure exploration process},
pages = {68--79},
}
Downloads: 0
{"_id":"RSZu2sJLF8v5XX6wt","bibbaseid":"sengupta-bhadauria-mohanty-lowcostsecurityawarehlsmethodology-2017","author_short":["Sengupta, A.","Bhadauria, S.","Mohanty, S. P."],"bibdata":{"bibtype":"article","type":"article","title":"Low-cost security aware HLS methodology","volume":"11","issn":"1751-8601","doi":"10.1049/iet-cdt.2016.0014","abstract":"Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a low-cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4%) through the proposed approach compared with a recent approach.","number":"2","journal":"IET Computers Digital Techniques","author":[{"propositions":[],"lastnames":["Sengupta"],"firstnames":["A."],"suffixes":[]},{"propositions":[],"lastnames":["Bhadauria"],"firstnames":["S."],"suffixes":[]},{"propositions":[],"lastnames":["Mohanty"],"firstnames":["S.","P."],"suffixes":[]}],"year":"2017","keywords":"IC, IP cores, Trojan secured high-level synthesis methodology, candidate datapath resource configuration, design process globalisation, design space, digital integrated circuits, encoding, hardware threats, high level synthesis, industrial property, integrated circuit design, intellectual property cores, invasive software, low-cost Trojan secured schedule, low-cost optimised dual modular redundant design, low-cost security aware HLS methodology, low-cost security-aware HLS approach, resource allocation, scheduling, third party vendors, user constraints, vendor allocation information, vendor allocation procedure exploration process","pages":"68–79","bibtex":"@article{sengupta_low-cost_2017,\n\ttitle = {Low-cost security aware {HLS} methodology},\n\tvolume = {11},\n\tissn = {1751-8601},\n\tdoi = {10.1049/iet-cdt.2016.0014},\n\tabstract = {Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a low-cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4\\%) through the proposed approach compared with a recent approach.},\n\tnumber = {2},\n\tjournal = {IET Computers Digital Techniques},\n\tauthor = {Sengupta, A. and Bhadauria, S. and Mohanty, S. P.},\n\tyear = {2017},\n\tkeywords = {IC, IP cores, Trojan secured high-level synthesis methodology, candidate datapath resource configuration, design process globalisation, design space, digital integrated circuits, encoding, hardware threats, high level synthesis, industrial property, integrated circuit design, intellectual property cores, invasive software, low-cost Trojan secured schedule, low-cost optimised dual modular redundant design, low-cost security aware HLS methodology, low-cost security-aware HLS approach, resource allocation, scheduling, third party vendors, user constraints, vendor allocation information, vendor allocation procedure exploration process},\n\tpages = {68--79},\n}\n\n","author_short":["Sengupta, A.","Bhadauria, S.","Mohanty, S. P."],"key":"sengupta_low-cost_2017","id":"sengupta_low-cost_2017","bibbaseid":"sengupta-bhadauria-mohanty-lowcostsecurityawarehlsmethodology-2017","role":"author","urls":{},"keyword":["IC","IP cores","Trojan secured high-level synthesis methodology","candidate datapath resource configuration","design process globalisation","design space","digital integrated circuits","encoding","hardware threats","high level synthesis","industrial property","integrated circuit design","intellectual property cores","invasive software","low-cost Trojan secured schedule","low-cost optimised dual modular redundant design","low-cost security aware HLS methodology","low-cost security-aware HLS approach","resource allocation","scheduling","third party vendors","user constraints","vendor allocation information","vendor allocation procedure exploration process"],"metadata":{"authorlinks":{}},"downloads":0,"html":""},"bibtype":"article","biburl":"https://bibbase.org/zotero/bxt101","dataSources":["Wsv2bQ4jPuc7qme8R"],"keywords":["ic","ip cores","trojan secured high-level synthesis methodology","candidate datapath resource configuration","design process globalisation","design space","digital integrated circuits","encoding","hardware threats","high level synthesis","industrial property","integrated circuit design","intellectual property cores","invasive software","low-cost trojan secured schedule","low-cost optimised dual modular redundant design","low-cost security aware hls methodology","low-cost security-aware hls approach","resource allocation","scheduling","third party vendors","user constraints","vendor allocation information","vendor allocation procedure exploration process"],"search_terms":["low","cost","security","aware","hls","methodology","sengupta","bhadauria","mohanty"],"title":"Low-cost security aware HLS methodology","year":2017}