Cyclic Obfuscation for Creating SAT-Unresolvable Circuits. Shamsi, K., Li, M., Meade, T., Zhao, Z., Pan, D. Z., & Jin, Y. In Proceedings of the on Great Lakes Symposium on VLSI 2017, of GLSVLSI '17, pages 173–178, Banff, Alberta, Canada, May, 2017. Association for Computing Machinery. ![Cyclic Obfuscation for Creating SAT-Unresolvable Circuits [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi abstract bibtex Logic locking and IC camouflaging are proactive circuit obfuscation methods that if proven secure can thwart hardware attacks such as reverse engineering and IP theft. However, the security of both these schemes is called into question by recent SAT based attacks. While a number of methods have been proposed in literature that exponentially increase the running time of such attacks, they are vulnerable to "findand-remove" attacks, and only slightly hide the circuit functionality. In this paper, we present a novel approach towards creating SAT attack resiliency based on creating densely cyclic obfuscated circuit topologies by adding dummy paths to the circuit. Our methodology is applicable to both IC camouflaging and logic locking. We demonstrate that cyclic logic locking creates SAT resilient circuits with 40% less area and 20% less delay compared to an insecure XOR/XNOR-obfuscation with the same key length. Furthermore, we show that cyclic IC camouflaging can be implemented at the layout level with no substrate area overhead and little delay and power overhead with respect to the original circuit.
@inproceedings{shamsi_cyclic_2017,
address = {Banff, Alberta, Canada},
series = {{GLSVLSI} '17},
title = {Cyclic {Obfuscation} for {Creating} {SAT}-{Unresolvable} {Circuits}},
isbn = {978-1-4503-4972-7},
url = {http://doi.org/10.1145/3060403.3060458},
doi = {10.1145/3060403.3060458},
abstract = {Logic locking and IC camouflaging are proactive circuit obfuscation methods that if proven secure can thwart hardware attacks such as reverse engineering and IP theft. However, the security of both these schemes is called into question by recent SAT based attacks. While a number of methods have been proposed in literature that exponentially increase the running time of such attacks, they are vulnerable to "findand-remove" attacks, and only slightly hide the circuit functionality. In this paper, we present a novel approach towards creating SAT attack resiliency based on creating densely cyclic obfuscated circuit topologies by adding dummy paths to the circuit. Our methodology is applicable to both IC camouflaging and logic locking. We demonstrate that cyclic logic locking creates SAT resilient circuits with 40\% less area and 20\% less delay compared to an insecure XOR/XNOR-obfuscation with the same key length. Furthermore, we show that cyclic IC camouflaging can be implemented at the layout level with no substrate area overhead and little delay and power overhead with respect to the original circuit.},
urldate = {2020-03-17},
booktitle = {Proceedings of the on {Great} {Lakes} {Symposium} on {VLSI} 2017},
publisher = {Association for Computing Machinery},
author = {Shamsi, Kaveh and Li, Meng and Meade, Travis and Zhao, Zheng and Pan, David Z. and Jin, Yier},
month = may,
year = {2017},
keywords = {circuit obfuscation, deobfuscation, ic camouflaging, ic decamouflaging, logic locking, sat attacks},
pages = {173--178},
}
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