ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips. Sharma, V., Agarwal, R., Gaur, M. S., Laxmi, V., & V., V. In Network and Parallel Computing, IFIP International Conference, NPC 2010, Zhengzhou, China, September 13-15, 2010. Proceedings, pages 481–490, 2010.
ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips [link]Paper  doi  bibtex   5 downloads  
@inproceedings{DBLP:conf/npc/SharmaAGLV10,
  author       = {Varsha Sharma and
                  Rekha Agarwal and
                  Manoj Singh Gaur and
                  Vijay Laxmi and
                  Vineetha V.},
  title        = {{ERA:} An Efficient Routing Algorithm for Power, Throughput and Latency
                  in Network-on-Chips},
  booktitle    = {Network and Parallel Computing, {IFIP} International Conference, {NPC}
                  2010, Zhengzhou, China, September 13-15, 2010. Proceedings},
  pages        = {481--490},
  year         = {2010},
  crossref     = {DBLP:conf/npc/2010},
  url          = {https://doi.org/10.1007/978-3-642-15672-4\_41},
  doi          = {10.1007/978-3-642-15672-4\_41},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/npc/SharmaAGLV10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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