@inproceedings{DBLP:conf/vdat/SharmaAGBL16,
  author       = {Ashish Sharma and
                  Ruby Ansar and
                  Manoj Singh Gaur and
                  Lava Bhargava and
                  Vijay Laxmi},
  title        = {Reducing {FIFO} buffer power using architectural alternatives at {RTL}},
  booktitle    = {20th International Symposium on {VLSI} Design and Test, {VDAT} 2016,
                  Guwahati, India, May 24-27, 2016},
  pages        = {1--2},
  year         = {2016},
  crossref     = {DBLP:conf/vdat/2016},
  url          = {https://doi.org/10.1109/ISVDAT.2016.8064897},
  doi          = {10.1109/ISVDAT.2016.8064897},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vdat/SharmaAGBL16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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