Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture

Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture. Sharma, A., Gaur, M. S., Bhargava, L., Laxmi, V., & Gupta, M. Microprocess. Microsystems, 91:104526, 2022.

Paper doi bibtex

@article{DBLP:journals/mam/SharmaGBLG22,
  author       = {Ashish Sharma and
                  Manoj Singh Gaur and
                  Lava Bhargava and
                  Vijay Laxmi and
                  Manoj Gupta},
  title        = {Pre-Silicon {NBTI} Delay-Aware Modeling of Network-on-Chip Router
                  Microarchitecture},
  journal      = {Microprocess. Microsystems},
  volume       = {91},
  pages        = {104526},
  year         = {2022},
  url          = {https://doi.org/10.1016/j.micpro.2022.104526},
  doi          = {10.1016/J.MICPRO.2022.104526},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/mam/SharmaGBLG22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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