Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands. Shekhar, N., Kalla, P., Meredith, M. B., & Enescu, F. In Formal Methods in Computer-Aided Design, 6th International Conference, FMCAD 2006, San Jose, California, USA, November 12-16, 2006, Proceedings, pages 179–186, 2006. Paper doi bibtex @inproceedings{DBLP:conf/fmcad/ShekharKME06,
author = {Namrata Shekhar and
Priyank Kalla and
M. Brandon Meredith and
Florian Enescu},
title = {Simulation Bounds for Equivalence Verification of Arithmetic Datapaths
with Finite Word-Length Operands},
booktitle = {Formal Methods in Computer-Aided Design, 6th International Conference,
{FMCAD} 2006, San Jose, California, USA, November 12-16, 2006, Proceedings},
pages = {179--186},
year = {2006},
crossref = {DBLP:conf/fmcad/2006},
url = {https://doi.org/10.1109/FMCAD.2006.30},
doi = {10.1109/FMCAD.2006.30},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/bib/conf/fmcad/ShekharKME06},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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