Fault resilient physical neural networks on a single chip. Shi, W., Wen, Y., Liu, Z., Zhao, X., Boumber, D., Vilalta, R., & Xu, L. In Chatha, K. S., Ernst, R., Raghunathan, A., & Iyer, R. R., editors, 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014, pages 24:1–24:10, 2014. ACM.
Paper doi bibtex @inproceedings{DBLP:conf/cases/ShiWLZBVX14,
author = {Weidong Shi and
Yuanfeng Wen and
Ziyi Liu and
Xi Zhao and
Dainis Boumber and
Ricardo Vilalta and
Lei Xu},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Fault resilient physical neural networks on a single chip},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {24:1--24:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656126},
doi = {10.1145/2656106.2656126},
timestamp = {Sat, 28 Mar 2020 15:18:43 +0100},
biburl = {https://dblp.org/rec/conf/cases/ShiWLZBVX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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