7.3 a 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a pe array and self-organizing map neural network. Shi, C., Yang, J., Han, Y., Cao, Z., Qin, Q., Liu, L., Wu, N., & Wang, Z. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, pages 128–129, 2014. IEEE. bibtex @inproceedings{shi20147,
title={7.3 a 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a pe array and self-organizing map neural network},
author={Shi, Cong and Yang, Jie and Han, Ye and Cao, Zhongxiang and Qin, Qi and Liu, Liyuan and Wu, Nan-Jian and Wang, Zhihua},
booktitle={Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International},
pages={128--129},
year={2014},
organization={IEEE}
}
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