@inproceedings{Shila2015FIDES-Enh,
	author = {Shila, Devu and Venugopalan, Vivek and Patterson, Cameron},
	booktitle = {IEEE High Performance Extreme Computing Conference (HPEC)},
	date-added = {2020-01-20 18:26:09 -0500},
	date-modified = {2020-01-20 18:26:09 -0500},
	keywords = {Security; authorisation;field programmable gate arrays;logic design;reconfigurable architectures;FIDES architecture;FPGA IP cores;FPGA application design process;FPGA application development process;HDL;IP core communication activities;Xilinx Zynq 7020 device;access control policies;anomaly detection capability;behavior learning techniques;bit-stream protection measures;embedding;fidelity enhancing security methodology;logic resources;minimal latency;netlist;nonsensitive IP cores;open source tools;overhead;reconfigurable based hardware systems;red-black system;sensitive IP cores;tag verification;third-party IP cores;trusted environment;Field programmable gate arrays;Hardware;IP networks;Monitoring;Tagging;Trojan horses;Design;FPGAs;Hardware Trojans;Security and Trust},
	month = sep,
	pages = {1-7},
	title = {{FIDES: Enhancing Trust in Reconfigurable Based Hardware Systems}},
	year = {2015},
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	Bdsk-Url-1 = {http://dx.doi.org/10.1109/HPEC.2015.7322483}}

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