@inProceedings{
 title = {Radio design for future wireless SoC platforms: An overview},
 type = {inProceedings},
 year = {2004},
 identifiers = {[object Object]},
 id = {80850182-9d2d-37f8-b1c4-5f6bac9f9206},
 created = {2017-12-04T05:35:01.398Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:35:01.398Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {As we move to third and fourth generation wireless providing higher data rates at shorter distances in "hotspots", future handhelds will be able to access different wireless infrastructures, e.g. UMTS and WLAN, from the same wireless device, be it a mobile phone, a PDA or a notebook. As a result SoC platforms for convergent 4G must address the challenge of increased complexity particularly as it pertains to the radio transceiver part of a chipset where power consumption and cost are the main differentiators. This paper presents an overview of the challenges faced in designing highly integrated radios in the context of 4G wireless communications. Aside from important issues such as multi antenna design and standards coexistence in the same SoC platform, we focus our overview on a few main thrusts that will be discussed in some details related to designing digitally programmable and con gurable ADCs, PLLs, analog baseband chains and RF front ends as well as techniques for packaging multi band radios and for achieving "rst pass" silicon success. © 2004 IEEE.},
 bibtype = {inProceedings},
 author = {Signell, S. and De Llera González, D.R. and Ismail, M.},
 booktitle = {Proceedings - Norchip}
}

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