Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. Singh, P., Asthana, V., Sithanandam, R., Bulusu, A., & Dasgupta, S. In VLSI Design, pages 411-414, 2014. IEEE Computer Society.
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Paper bibtex @inproceedings{conf/vlsid/SinghASBD14,
added-at = {2015-04-20T00:00:00.000+0200},
author = {Singh, Parmanand and Asthana, Vivek and Sithanandam, Radhakrishnan and Bulusu, Anand and Dasgupta, Sudeb},
biburl = {http://www.bibsonomy.org/bibtex/2274bf3fac0d90e1420462ade7c283e29/dblp},
booktitle = {VLSI Design},
crossref = {conf/vlsid/2014},
ee = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2014.77},
interhash = {88a83f00e467e8cf77787ed676da591c},
intrahash = {274bf3fac0d90e1420462ade7c283e29},
isbn = {978-1-4799-2513-1},
keywords = {dblp},
pages = {411-414},
publisher = {IEEE Computer Society},
timestamp = {2015-06-18T10:52:11.000+0200},
title = {Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor.},
url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2014.html#SinghASBD14},
year = 2014
}
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