A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC. Siragusa, E. & Galton, I. In pages 452--538, 2004. IEEE.
A digitally enhanced 1.8 V 15 b 40 MS/s CMOS pipelined ADC [link]Paper  doi  bibtex   
@inproceedings{siragusa_digitally_2004-1,
	title = {A digitally enhanced 1.8 {V} 15 b 40 {MS}/s {CMOS} pipelined {ADC}},
	isbn = {978-0-7803-8267-1},
	url = {http://ieeexplore.ieee.org/document/1332789/},
	doi = {10.1109/ISSCC.2004.1332789},
	urldate = {2017-05-10TZ},
	publisher = {IEEE},
	author = {Siragusa, E. and Galton, I.},
	year = {2004},
	pages = {452--538}
}

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