A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. Siragusa, E. & Galton, I. Solid-State Circuits, IEEE Journal of, 39(12):2126--2138, 2004.
bibtex   
@article{siragusa_digitally_2004,
	title = {A digitally enhanced 1.8-{V} 15-bit 40-{MSample}/s {CMOS} pipelined {ADC}},
	volume = {39},
	number = {12},
	journal = {Solid-State Circuits, IEEE Journal of},
	author = {Siragusa, Eric and Galton, Ian},
	year = {2004},
	pages = {2126--2138}
}

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