Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS. Sk, G., Gupta, K., Calhoun, B. H., & Pandey, N. IEEE Transactions on Circuits and Systems I-regular Papers, 2019. ![Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper bibtex @article{563,
author = {Gupta Sk and Kirti Gupta and Benton H. Calhoun and Neeta Pandey},
title = {Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS},
year = {2019},
journal = {IEEE Transactions on Circuits and Systems I-regular Papers},
url = {https://doi.org/10.1109/tcsi.2018.2876785}
}
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