PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning. Song, L., Qian, X., Li, H., & Chen, Y. In 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017, pages 541–552, 2017. IEEE Computer Society.
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/hpca/SongQ0C17,
  author    = {Linghao Song and
               Xuehai Qian and
               Hai Li and
               Yiran Chen},
  title     = {PipeLayer: {A} Pipelined ReRAM-Based Accelerator for Deep Learning},
  booktitle = {2017 {IEEE} International Symposium on High Performance Computer Architecture,
               {HPCA} 2017, Austin, TX, USA, February 4-8, 2017},
  pages     = {541--552},
  publisher = {{IEEE} Computer Society},
  year      = {2017},
  url       = {https://doi.org/10.1109/HPCA.2017.55},
  doi       = {10.1109/HPCA.2017.55},
  timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/hpca/SongQ0C17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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