A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. Srinivasan, K. & Chatha, K. S. In ISQED, pages 352-357, 2006. IEEE Computer Society.
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. [link]Link  A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. [link]Paper  bibtex   
@inproceedings{conf/isqed/SrinivasanC06,
  added-at = {2014-09-27T00:00:00.000+0200},
  author = {Srinivasan, Krishnan and Chatha, Karam S.},
  biburl = {http://www.bibsonomy.org/bibtex/24909b7128a30e09e2259dfc3a675a672/dblp},
  booktitle = {ISQED},
  crossref = {conf/isqed/2006},
  ee = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.13},
  interhash = {bf91ca3cb312070b3b3d505aec09b2aa},
  intrahash = {4909b7128a30e09e2259dfc3a675a672},
  isbn = {0-7695-2523-7},
  keywords = {dblp},
  pages = {352-357},
  publisher = {IEEE Computer Society},
  timestamp = {2015-06-18T23:42:04.000+0200},
  title = {A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures.},
  url = {http://dblp.uni-trier.de/db/conf/isqed/isqed2006.html#SrinivasanC06},
  year = 2006
}
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