An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. Srinivasan, K. & Chatha, K. S. In VLSI Design, pages 255-260, 2004. IEEE Computer Society.
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. [link]Link  An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. [link]Paper  bibtex   
@inproceedings{conf/vlsid/SrinivasanC04,
  added-at = {2015-04-20T00:00:00.000+0200},
  author = {Srinivasan, Krishnan and Chatha, Karam S.},
  biburl = {http://www.bibsonomy.org/bibtex/2ceb0babb93a350cf16f07903eb84023b/dblp},
  booktitle = {VLSI Design},
  crossref = {conf/vlsid/2004},
  ee = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2004.1260933},
  interhash = {f9eec287355a0d8c321e1720a1c9ae4e},
  intrahash = {ceb0babb93a350cf16f07903eb84023b},
  isbn = {0-7695-2072-3},
  keywords = {dblp},
  pages = {255-260},
  publisher = {IEEE Computer Society},
  timestamp = {2015-06-18T10:53:59.000+0200},
  title = {An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures.},
  url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2004.html#SrinivasanC04},
  year = 2004
}

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