System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. Srinivasan, K., Telkar, N., Ramamurthi, V., & Chatha, K. S. In ISVLSI, pages 39-45, 2004. IEEE Computer Society.
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. [link]Link  System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. [link]Paper  bibtex   
@inproceedings{conf/isvlsi/SrinivasanTRC04,
  added-at = {2015-05-26T00:00:00.000+0200},
  author = {Srinivasan, Krishnan and Telkar, Nagender and Ramamurthi, Vijay and Chatha, Karam S.},
  biburl = {http://www.bibsonomy.org/bibtex/2a963e721ecb2c3a5707067a58ad563ad/dblp},
  booktitle = {ISVLSI},
  crossref = {conf/isvlsi/2004},
  ee = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339506},
  interhash = {15bc173d045ac94cac918082cf1e6d54},
  intrahash = {a963e721ecb2c3a5707067a58ad563ad},
  isbn = {0-7695-2097-9},
  keywords = {dblp},
  pages = {39-45},
  publisher = {IEEE Computer Society},
  timestamp = {2015-06-18T19:47:03.000+0200},
  title = {System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.},
  url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2004.html#SrinivasanTRC04},
  year = 2004
}

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