System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. Srinivasan, K., Telkar, N., Ramamurthi, V., & Chatha, K. S. In ISVLSI, pages 39-45, 2004. IEEE Computer Society. Link Paper bibtex @inproceedings{conf/isvlsi/SrinivasanTRC04,
added-at = {2015-05-26T00:00:00.000+0200},
author = {Srinivasan, Krishnan and Telkar, Nagender and Ramamurthi, Vijay and Chatha, Karam S.},
biburl = {http://www.bibsonomy.org/bibtex/2a963e721ecb2c3a5707067a58ad563ad/dblp},
booktitle = {ISVLSI},
crossref = {conf/isvlsi/2004},
ee = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339506},
interhash = {15bc173d045ac94cac918082cf1e6d54},
intrahash = {a963e721ecb2c3a5707067a58ad563ad},
isbn = {0-7695-2097-9},
keywords = {dblp},
pages = {39-45},
publisher = {IEEE Computer Society},
timestamp = {2015-06-18T19:47:03.000+0200},
title = {System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.},
url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2004.html#SrinivasanTRC04},
year = 2004
}
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{"_id":"wKqK9RZfFtGejw6B6","bibbaseid":"srinivasan-telkar-ramamurthi-chatha-systemleveldesigntechniquesforthroughputandpoweroptimizationofmultiprocessorsocarchitectures-2004","downloads":0,"creationDate":"2016-10-11T08:28:53.689Z","title":"System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.","author_short":["Srinivasan, K.","Telkar, N.","Ramamurthi, V.","Chatha, K. S."],"year":2004,"bibtype":"inproceedings","biburl":"http://www.bibsonomy.org/bib/author/krishnan?items=1000","bibdata":{"bibtype":"inproceedings","type":"inproceedings","added-at":"2015-05-26T00:00:00.000+0200","author":[{"propositions":[],"lastnames":["Srinivasan"],"firstnames":["Krishnan"],"suffixes":[]},{"propositions":[],"lastnames":["Telkar"],"firstnames":["Nagender"],"suffixes":[]},{"propositions":[],"lastnames":["Ramamurthi"],"firstnames":["Vijay"],"suffixes":[]},{"propositions":[],"lastnames":["Chatha"],"firstnames":["Karam","S."],"suffixes":[]}],"biburl":"http://www.bibsonomy.org/bibtex/2a963e721ecb2c3a5707067a58ad563ad/dblp","booktitle":"ISVLSI","crossref":"conf/isvlsi/2004","ee":"http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339506","interhash":"15bc173d045ac94cac918082cf1e6d54","intrahash":"a963e721ecb2c3a5707067a58ad563ad","isbn":"0-7695-2097-9","keywords":"dblp","pages":"39-45","publisher":"IEEE Computer Society","timestamp":"2015-06-18T19:47:03.000+0200","title":"System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.","url":"http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2004.html#SrinivasanTRC04","year":"2004","bibtex":"@inproceedings{conf/isvlsi/SrinivasanTRC04,\n added-at = {2015-05-26T00:00:00.000+0200},\n author = {Srinivasan, Krishnan and Telkar, Nagender and Ramamurthi, Vijay and Chatha, Karam S.},\n biburl = {http://www.bibsonomy.org/bibtex/2a963e721ecb2c3a5707067a58ad563ad/dblp},\n booktitle = {ISVLSI},\n crossref = {conf/isvlsi/2004},\n ee = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339506},\n interhash = {15bc173d045ac94cac918082cf1e6d54},\n intrahash = {a963e721ecb2c3a5707067a58ad563ad},\n isbn = {0-7695-2097-9},\n keywords = {dblp},\n pages = {39-45},\n publisher = {IEEE Computer Society},\n timestamp = {2015-06-18T19:47:03.000+0200},\n title = {System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures.},\n url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2004.html#SrinivasanTRC04},\n year = 2004\n}\n\n","author_short":["Srinivasan, K.","Telkar, N.","Ramamurthi, V.","Chatha, K. S."],"key":"conf/isvlsi/SrinivasanTRC04","id":"conf/isvlsi/SrinivasanTRC04","bibbaseid":"srinivasan-telkar-ramamurthi-chatha-systemleveldesigntechniquesforthroughputandpoweroptimizationofmultiprocessorsocarchitectures-2004","role":"author","urls":{"Link":"http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2004.1339506","Paper":"http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2004.html#SrinivasanTRC04"},"keyword":["dblp"],"downloads":0},"search_terms":["system","level","design","techniques","throughput","power","optimization","multiprocessor","soc","architectures","srinivasan","telkar","ramamurthi","chatha"],"keywords":["dblp"],"authorIDs":[],"dataSources":["xsmEhpcqYQxeyggwv"]}