Circuit-level techniques to control gate leakage for sub-100nm CMOS. Stan, M. International Symposium on Low Power Electronics and Design - ISLPED, Unknown Month, 2002.
Circuit-level techniques to control gate leakage for sub-100nm CMOS [link]Paper  bibtex   
@article{0000-0003-0577-9976:72334402,
 author = {Mircea Stan},
 journal = {International Symposium on Low Power Electronics and Design - ISLPED},
 month = {Unknown Month},
 title = {Circuit-level techniques to control gate leakage for sub-100nm CMOS},
 url = {https://publons.com/publon/15508602/},
 year = {2002}
}

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