Stampede 2: The Evolution of an XSEDE supercomputer. Stanzione, D., Barth, B., Gaffney, N., Gaither, K., Mehringer, S., Hempel, C., Wernert, E., Minyard, T., Tufo, H., Panda, D., & Teller, P. In Proceedings of the Practice and Experience in Advanced Research Computing 2017 on Sustainability, Success and Impact (PEARC17), volume Part F1287, pages 8, 2017. Association for Computing Machinery. ![Stampede 2: The Evolution of an XSEDE supercomputer [link]](https://bibbase.org/img/filetypes/link.svg "link")
Website doi abstract bibtex The Stampede 1 supercomputer was a tremendous success as an XSEDE resource, providing more than eight million successful computational simulations and data analysis jobs to more than ten thousand users. In addition, Stampede 1 introduced new technology that began to move users towards many core processors. As Stampede 1 reaches the end of its production life, it is being replaced in phases by a new supercomputer, Stampede 2, that will not only take up much of the original system's workload, but continue the bridge to technologies on the path to exascale computing. This paper provides a brief summary of the experiences of Stampede 1, and details the design and architecture of Stampede 2. Early results are presented from a subset of Intel Knights Landing nodes that are bridging between the two systems. © 2017 Association for Computing Machinery.
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title = {Stampede 2: The Evolution of an XSEDE supercomputer},
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abstract = {The Stampede 1 supercomputer was a tremendous success as an XSEDE resource, providing more than eight million successful computational simulations and data analysis jobs to more than ten thousand users. In addition, Stampede 1 introduced new technology that began to move users towards many core processors. As Stampede 1 reaches the end of its production life, it is being replaced in phases by a new supercomputer, Stampede 2, that will not only take up much of the original system's workload, but continue the bridge to technologies on the path to exascale computing. This paper provides a brief summary of the experiences of Stampede 1, and details the design and architecture of Stampede 2. Early results are presented from a subset of Intel Knights Landing nodes that are bridging between the two systems. © 2017 Association for Computing Machinery.},
bibtype = {inproceedings},
author = {Stanzione, D and Barth, B and Gaffney, N and Gaither, K and Mehringer, S and Hempel, C and Wernert, E and Minyard, T and Tufo, H and Panda, D and Teller, P},
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