@article{journals/jcp/SterponeV06,
  added-at = {2020-09-15T00:00:00.000+0200},
  author = {Sterpone, Luca and Violante, Massimo},
  biburl = {https://www.bibsonomy.org/bibtex/2f82df6265bfd46cf305c84346cacf509/dblp},
  ee = {https://doi.org/10.4304/jcp.1.1.22-30},
  interhash = {29739117407a8b1b69b14c945c8900ba},
  intrahash = {f82df6265bfd46cf305c84346cacf509},
  journal = {J. Comput.},
  keywords = {dblp},
  number = 1,
  pages = {22-30},
  timestamp = {2020-09-16T11:46:22.000+0200},
  title = {Hardening FPGA-based Systems Against SEUs: A New Design Methodology.},
  url = {http://dblp.uni-trier.de/db/journals/jcp/jcp1.html#SterponeV06},
  volume = 1,
  year = 2006
}

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