Yield optimization of analog MOS integrated circuits including transistor mismatch. Su, H., Michael, C., & Ismail, M. In Proceedings - IEEE International Symposium on Circuits and Systems, volume 3, 1993. abstract bibtex With the aid of the SMOS (Statistical MOS) model, it is presently possible to simulate random device mismatch effects on the circuit performance. This paper presents two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers. The goal of these optimizations is for the user to determine the optimal circuit modification to achieve a user specified parametric yield as well as the nominal circuit specifications. The optimization algorithms use steepest descent method and experiment design with the response surface methodology (RSM). Area optimization of a Miller compensated operational amplifier is used as an example.
@inProceedings{
title = {Yield optimization of analog MOS integrated circuits including transistor mismatch},
type = {inProceedings},
year = {1993},
identifiers = {[object Object]},
volume = {3},
id = {80bdd4ea-271a-3dc0-958b-63d42bfd5f2a},
created = {2017-12-04T05:35:00.530Z},
file_attached = {false},
profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
last_modified = {2017-12-04T05:35:00.530Z},
read = {false},
starred = {false},
authored = {true},
confirmed = {false},
hidden = {false},
private_publication = {false},
abstract = {With the aid of the SMOS (Statistical MOS) model, it is presently possible to simulate random device mismatch effects on the circuit performance. This paper presents two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers. The goal of these optimizations is for the user to determine the optimal circuit modification to achieve a user specified parametric yield as well as the nominal circuit specifications. The optimization algorithms use steepest descent method and experiment design with the response surface methodology (RSM). Area optimization of a Miller compensated operational amplifier is used as an example.},
bibtype = {inProceedings},
author = {Su, Hua and Michael, Christopher and Ismail, Mohammed},
booktitle = {Proceedings - IEEE International Symposium on Circuits and Systems}
}
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{"_id":"mn7Csy2ujyNocHDQK","bibbaseid":"su-michael-ismail-yieldoptimizationofanalogmosintegratedcircuitsincludingtransistormismatch-1993","downloads":0,"creationDate":"2018-11-02T20:16:34.690Z","title":"Yield optimization of analog MOS integrated circuits including transistor mismatch","author_short":["Su, H.","Michael, C.","Ismail, M."],"year":1993,"bibtype":"inProceedings","biburl":null,"bibdata":{"title":"Yield optimization of analog MOS integrated circuits including transistor mismatch","type":"inProceedings","year":"1993","identifiers":"[object Object]","volume":"3","id":"80bdd4ea-271a-3dc0-958b-63d42bfd5f2a","created":"2017-12-04T05:35:00.530Z","file_attached":false,"profile_id":"99d7e05e-a704-3549-ada2-dfc74a2d55ec","last_modified":"2017-12-04T05:35:00.530Z","read":false,"starred":false,"authored":"true","confirmed":false,"hidden":false,"private_publication":false,"abstract":"With the aid of the SMOS (Statistical MOS) model, it is presently possible to simulate random device mismatch effects on the circuit performance. This paper presents two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers. The goal of these optimizations is for the user to determine the optimal circuit modification to achieve a user specified parametric yield as well as the nominal circuit specifications. The optimization algorithms use steepest descent method and experiment design with the response surface methodology (RSM). Area optimization of a Miller compensated operational amplifier is used as an example.","bibtype":"inProceedings","author":"Su, Hua and Michael, Christopher and Ismail, Mohammed","booktitle":"Proceedings - IEEE International Symposium on Circuits and Systems","bibtex":"@inProceedings{\n title = {Yield optimization of analog MOS integrated circuits including transistor mismatch},\n type = {inProceedings},\n year = {1993},\n identifiers = {[object Object]},\n volume = {3},\n id = {80bdd4ea-271a-3dc0-958b-63d42bfd5f2a},\n created = {2017-12-04T05:35:00.530Z},\n file_attached = {false},\n profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},\n last_modified = {2017-12-04T05:35:00.530Z},\n read = {false},\n starred = {false},\n authored = {true},\n confirmed = {false},\n hidden = {false},\n private_publication = {false},\n abstract = {With the aid of the SMOS (Statistical MOS) model, it is presently possible to simulate random device mismatch effects on the circuit performance. This paper presents two different optimization algorithms, which, together with the SMOS model, can create an efficient CAD environment for integrated circuit designers. The goal of these optimizations is for the user to determine the optimal circuit modification to achieve a user specified parametric yield as well as the nominal circuit specifications. The optimization algorithms use steepest descent method and experiment design with the response surface methodology (RSM). Area optimization of a Miller compensated operational amplifier is used as an example.},\n bibtype = {inProceedings},\n author = {Su, Hua and Michael, Christopher and Ismail, Mohammed},\n booktitle = {Proceedings - IEEE International Symposium on Circuits and Systems}\n}","author_short":["Su, H.","Michael, C.","Ismail, M."],"bibbaseid":"su-michael-ismail-yieldoptimizationofanalogmosintegratedcircuitsincludingtransistormismatch-1993","role":"author","urls":{},"downloads":0,"html":""},"search_terms":["yield","optimization","analog","mos","integrated","circuits","including","transistor","mismatch","su","michael","ismail"],"keywords":[],"authorIDs":[]}