{"_id":"wtRRgBe22tvZGHbKk","bibbaseid":"su-yu-yasin-ciesielski-formalverificationoftruncatedmultipliersusingalgebraicapproachandresynthesis-2017","authorIDs":["5ce6fb5226c0fcda0100030c","5dcdc5f178619fde010000b3"],"author_short":["Su, T.","Yu, C.","Yasin, A.","Ciesielski, M. J."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Tiankai"],"propositions":[],"lastnames":["Su"],"suffixes":[]},{"firstnames":["Cunxi"],"propositions":[],"lastnames":["Yu"],"suffixes":[]},{"firstnames":["Atif"],"propositions":[],"lastnames":["Yasin"],"suffixes":[]},{"firstnames":["Maciej","J."],"propositions":[],"lastnames":["Ciesielski"],"suffixes":[]}],"title":"Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis","booktitle":"2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017","pages":"415–420","year":"2017","crossref":"DBLP:conf/isvlsi/2017","url":"https://doi.org/10.1109/ISVLSI.2017.79","doi":"10.1109/ISVLSI.2017.79","timestamp":"Wed, 16 Oct 2019 14:14:54 +0200","biburl":"https://dblp.org/rec/bib/conf/isvlsi/SuYYC17","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@inproceedings{DBLP:conf/isvlsi/SuYYC17,\n author = {Tiankai Su and\n Cunxi Yu and\n Atif Yasin and\n Maciej J. Ciesielski},\n title = {Formal Verification of Truncated Multipliers Using Algebraic Approach\n and Re-Synthesis},\n booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,\n Bochum, Germany, July 3-5, 2017},\n pages = {415--420},\n year = {2017},\n crossref = {DBLP:conf/isvlsi/2017},\n url = {https://doi.org/10.1109/ISVLSI.2017.79},\n doi = {10.1109/ISVLSI.2017.79},\n timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},\n biburl = {https://dblp.org/rec/bib/conf/isvlsi/SuYYC17},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Su, T.","Yu, C.","Yasin, A.","Ciesielski, M. J."],"key":"DBLP:conf/isvlsi/SuYYC17","id":"DBLP:conf/isvlsi/SuYYC17","bibbaseid":"su-yu-yasin-ciesielski-formalverificationoftruncatedmultipliersusingalgebraicapproachandresynthesis-2017","role":"author","urls":{"Paper":"https://doi.org/10.1109/ISVLSI.2017.79"},"downloads":0,"html":""},"bibtype":"inproceedings","biburl":"https://ycunxi.github.io/utah-csl/bibtex/all.bib","creationDate":"2019-05-23T19:58:10.237Z","downloads":0,"keywords":["dblp"],"search_terms":["formal","verification","truncated","multipliers","using","algebraic","approach","synthesis","su","yu","yasin","ciesielski"],"title":"Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis","year":2017,"dataSources":["L6BLFSB28hKk5Nt67"]}