Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis. Su, T., Yu, C., Yasin, A., & Ciesielski, M. J. In 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, Germany, July 3-5, 2017, pages 415–420, 2017.
Formal Verification of Truncated Multipliers Using Algebraic Approach and Re-Synthesis [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/isvlsi/SuYYC17,
  author    = {Tiankai Su and
               Cunxi Yu and
               Atif Yasin and
               Maciej J. Ciesielski},
  title     = {Formal Verification of Truncated Multipliers Using Algebraic Approach
               and Re-Synthesis},
  booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
               Bochum, Germany, July 3-5, 2017},
  pages     = {415--420},
  year      = {2017},
  crossref  = {DBLP:conf/isvlsi/2017},
  url       = {https://doi.org/10.1109/ISVLSI.2017.79},
  doi       = {10.1109/ISVLSI.2017.79},
  timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/SuYYC17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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