A Scalable Synthesis Methodology for Application-Specific Processors. Sun, F., Ravi, S., Raghunathan, A., & Jha, N. K. IEEE Trans. VLSI Syst., 14(11):1175–1188, 2006.
A Scalable Synthesis Methodology for Application-Specific Processors [link]Paper  doi  bibtex   
@article{DBLP:journals/tvlsi/SunRRJ06,
  author    = {Fei Sun and
               Srivaths Ravi and
               Anand Raghunathan and
               Niraj K. Jha},
  title     = {A Scalable Synthesis Methodology for Application-Specific Processors},
  journal   = {{IEEE} Trans. {VLSI} Syst.},
  volume    = {14},
  number    = {11},
  pages     = {1175--1188},
  year      = {2006},
  url       = {https://doi.org/10.1109/TVLSI.2006.886410},
  doi       = {10.1109/TVLSI.2006.886410},
  timestamp = {Thu, 18 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tvlsi/SunRRJ06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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