Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. Sun, F., Ravi, S., Raghunathan, A., & Jha, N. K. In 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pages 473–476, 2006.

Paper doi bibtex

@inproceedings{DBLP:conf/vlsid/SunRRJ06,
  author    = {Fei Sun and
               Srivaths Ravi and
               Anand Raghunathan and
               Niraj K. Jha},
  title     = {Hybrid Custom Instruction and Co-Processor Synthesis Methodology for
               Extensible Processors},
  booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
               3-7 January 2006, Hyderabad, India},
  pages     = {473--476},
  year      = {2006},
  crossref  = {DBLP:conf/vlsid/2006},
  url       = {https://doi.org/10.1109/VLSID.2006.100},
  doi       = {10.1109/VLSID.2006.100},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/SunRRJ06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

Downloads: 0

{"_id":"deJsJk4iPCNbZNWo3","bibbaseid":"sun-ravi-raghunathan-jha-hybridcustominstructionandcoprocessorsynthesismethodologyforextensibleprocessors-2006","downloads":0,"creationDate":"2018-06-20T07:11:31.639Z","title":"Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors","author_short":["Sun, F.","Ravi, S.","Raghunathan, A.","Jha, N. K."],"year":2006,"bibtype":"inproceedings","biburl":"https://dblp.org/pid/74/3747.bib","bibdata":{"bibtype":"inproceedings","type":"inproceedings","author":[{"firstnames":["Fei"],"propositions":[],"lastnames":["Sun"],"suffixes":[]},{"firstnames":["Srivaths"],"propositions":[],"lastnames":["Ravi"],"suffixes":[]},{"firstnames":["Anand"],"propositions":[],"lastnames":["Raghunathan"],"suffixes":[]},{"firstnames":["Niraj","K."],"propositions":[],"lastnames":["Jha"],"suffixes":[]}],"title":"Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors","booktitle":"19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India","pages":"473–476","year":"2006","crossref":"DBLP:conf/vlsid/2006","url":"https://doi.org/10.1109/VLSID.2006.100","doi":"10.1109/VLSID.2006.100","timestamp":"Tue, 23 May 2017 01:00:00 +0200","biburl":"https://dblp.org/rec/bib/conf/vlsid/SunRRJ06","bibsource":"dblp computer science bibliography, https://dblp.org","bibtex":"@inproceedings{DBLP:conf/vlsid/SunRRJ06,\n author = {Fei Sun and\n Srivaths Ravi and\n Anand Raghunathan and\n Niraj K. Jha},\n title = {Hybrid Custom Instruction and Co-Processor Synthesis Methodology for\n Extensible Processors},\n booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),\n 3-7 January 2006, Hyderabad, India},\n pages = {473--476},\n year = {2006},\n crossref = {DBLP:conf/vlsid/2006},\n url = {https://doi.org/10.1109/VLSID.2006.100},\n doi = {10.1109/VLSID.2006.100},\n timestamp = {Tue, 23 May 2017 01:00:00 +0200},\n biburl = {https://dblp.org/rec/bib/conf/vlsid/SunRRJ06},\n bibsource = {dblp computer science bibliography, https://dblp.org}\n}\n\n","author_short":["Sun, F.","Ravi, S.","Raghunathan, A.","Jha, N. K."],"key":"DBLP:conf/vlsid/SunRRJ06","id":"DBLP:conf/vlsid/SunRRJ06","bibbaseid":"sun-ravi-raghunathan-jha-hybridcustominstructionandcoprocessorsynthesismethodologyforextensibleprocessors-2006","role":"author","urls":{"Paper":"https://doi.org/10.1109/VLSID.2006.100"},"downloads":0},"search_terms":["hybrid","custom","instruction","processor","synthesis","methodology","extensible","processors","sun","ravi","raghunathan","jha"],"keywords":[],"authorIDs":[],"dataSources":["QATSsZPCAGgNRpLA3"]}