Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. Tan, B., Karri, R., Limaye, N., Sengupta, A., Sinanoglu, O., Rahman, M. M., Bhunia, S., Duvalsaint, D., D., R., Blanton, Rezaei, A., Shen, Y., Zhou, H., Li, L., Orailoglu, A., Han, Z., Benedetti, A., Brignone, L., Yasin, M., Rajendran, J., Zuzak, M., Srivastava, A., Guin, U., Karfa, C., Basu, K., Menon, V. V., French, M., Song, P., Stellari, F., Nam, G., Gadfort, P., Althoff, A., Tostenrude, J., Fazzari, S., Breckenfeld, E., & Plaks, K. June, 2020.
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking [link]Paper  abstract   bibtex   2 downloads  
Integrated circuits (ICs) are the foundation of all computing systems. They comprise high-value hardware intellectual property (IP) that are at risk of piracy, reverse-engineering, and modifications while making their way through the geographically-distributed IC supply chain. On the frontier of hardware security are various design-for-trust techniques that claim to protect designs from untrusted entities across the design flow. Logic locking is one technique that promises protection from the gamut of threats in IC manufacturing. In this work, we perform a critical review of logic locking techniques in the literature, and expose several shortcomings. Taking inspiration from other cybersecurity competitions, we devise a community-led benchmarking exercise to address the evaluation deficiencies. In reflecting on this process, we shed new light on deficiencies in evaluation of logic locking and reveal important future directions. The lessons learned can guide future endeavors in other areas of hardware security.
@misc{tan_benchmarking_2020,
	title = {Benchmarking at the {Frontier} of {Hardware} {Security}: {Lessons} from {Logic} {Locking}},
	copyright = {All rights reserved},
	shorttitle = {Benchmarking at the {Frontier} of {Hardware} {Security}},
	url = {http://arxiv.org/abs/2006.06806},
	abstract = {Integrated circuits (ICs) are the foundation of all computing systems. They comprise high-value hardware intellectual property (IP) that are at risk of piracy, reverse-engineering, and modifications while making their way through the geographically-distributed IC supply chain. On the frontier of hardware security are various design-for-trust techniques that claim to protect designs from untrusted entities across the design flow. Logic locking is one technique that promises protection from the gamut of threats in IC manufacturing. In this work, we perform a critical review of logic locking techniques in the literature, and expose several shortcomings. Taking inspiration from other cybersecurity competitions, we devise a community-led benchmarking exercise to address the evaluation deficiencies. In reflecting on this process, we shed new light on deficiencies in evaluation of logic locking and reveal important future directions. The lessons learned can guide future endeavors in other areas of hardware security.},
	urldate = {2020-06-20},
	author = {Tan, Benjamin and Karri, Ramesh and Limaye, Nimisha and Sengupta, Abhrajit and Sinanoglu, Ozgur and Rahman, Md Moshiur and Bhunia, Swarup and Duvalsaint, Danielle and D., R. and {Blanton} and Rezaei, Amin and Shen, Yuanqi and Zhou, Hai and Li, Leon and Orailoglu, Alex and Han, Zhaokun and Benedetti, Austin and Brignone, Luciano and Yasin, Muhammad and Rajendran, Jeyavijayan and Zuzak, Michael and Srivastava, Ankur and Guin, Ujjwal and Karfa, Chandan and Basu, Kanad and Menon, Vivek V. and French, Matthew and Song, Peilin and Stellari, Franco and Nam, Gi-Joon and Gadfort, Peter and Althoff, Alric and Tostenrude, Joseph and Fazzari, Saverio and Breckenfeld, Eric and Plaks, Kenneth},
	month = jun,
	year = {2020},
	keywords = {Computer Science - Cryptography and Security},
}
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