@inProceedings{
 title = {A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers},
 type = {inProceedings},
 year = {2002},
 identifiers = {[object Object]},
 volume = {4},
 id = {94df69cd-bbe5-37ee-be98-28d0ca2cc2f5},
 created = {2017-12-04T05:34:56.022Z},
 file_attached = {false},
 profile_id = {99d7e05e-a704-3549-ada2-dfc74a2d55ec},
 last_modified = {2017-12-04T05:34:56.022Z},
 read = {false},
 starred = {false},
 authored = {true},
 confirmed = {false},
 hidden = {false},
 private_publication = {false},
 abstract = {The loop bandwidth of PLL frequency synthesizers involves design tradeoffs between the lock time and reference feedthrough. The adaptive PLL solves the problem by increasing the bandwidth in the acquiring stage for faster lock speed and reducing the bandwidth after the loop locks for lower spur level. However, the loop bandwidth in the speedup mode is constrained to approximately 1/10 of the reference frequency for stability considerations. In this paper, the theoretical bandwidth limitation is explored with a simple nonlinear sampling delay model. A new adaptation scheme is proposed that extends the loop bandwidth enhancement by adaptively controlling the reference frequency in a gear-shifting approach. In the speedup mode, the loop bandwidth is enhanced by up to 64 times due to the increased reference frequency, resulting in a fast settling time of 229μs to within 20kHz for a 80MHz frequency step in a 200kHz channel spacing synthesizer.},
 bibtype = {inProceedings},
 author = {Tang, Y. and Ismail, M. and Bibyk, S.},
 booktitle = {Proceedings - IEEE International Symposium on Circuits and Systems}
}

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