Design and implementation of a high speed digital FIR filter using unfolding. Thakral, S., Goswami, D., Sharma, R., Prasanna, C., & Joshi, A. In 2016 IEEE 7th Power India International Conference, PIICON 2016, 2017. doi abstract bibtex © 2016 IEEE. The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier and with low propagation delay carry increment adder. In the proposed design, the FIR filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases. The propagation delay is reduced to almost three times in FIR filter by using faster adder, high speed multiplier and unfolding transformation technique. We have synthesized the proposed design on Xilinx ISE 14.7 with Virtex IV FPGA family. The obtained results also confirm the faster performance of the FIR filter.
@inproceedings{
title = {Design and implementation of a high speed digital FIR filter using unfolding},
type = {inproceedings},
year = {2017},
keywords = {Carry Increment adder,FIR filter,Propagation delay,Unfolding,Vedic multiplier},
id = {9a889f74-a5fa-3e63-8152-d48ff28668b6},
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last_modified = {2018-09-06T11:22:40.705Z},
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abstract = {© 2016 IEEE. The paper presents the design and implementation of a high speed digital Finite Impulse Response (FIR) filter using unfolding transformation technique. FIR Filter has widespread applications in signal processing such as image processing, biomedical signal processing, high speed communication systems, noise elimination and many more. The speed of FIR filter can be improved with high speed vedic multiplier and with low propagation delay carry increment adder. In the proposed design, the FIR filter is unfolded by a factor 3 which results in scheduling the filter to a smaller iteration period and along with this throughput of the filter also increases. The propagation delay is reduced to almost three times in FIR filter by using faster adder, high speed multiplier and unfolding transformation technique. We have synthesized the proposed design on Xilinx ISE 14.7 with Virtex IV FPGA family. The obtained results also confirm the faster performance of the FIR filter.},
bibtype = {inproceedings},
author = {Thakral, S. and Goswami, D. and Sharma, R. and Prasanna, C.K. and Joshi, A.M.},
doi = {10.1109/POWERI.2016.8077361},
booktitle = {2016 IEEE 7th Power India International Conference, PIICON 2016}
}
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