Benchmarking Large Language Models for Automated Verilog RTL Code Generation. Thakur, S., Ahmad, B., Fan, Z., Pearce, H., Tan, B., Karri, R., Dolan-Gavitt, B., & Garg, S. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1–6, Antwerp, Belgium, April, 2023. IEEE. ![Benchmarking Large Language Models for Automated Verilog RTL Code Generation [link]](https://bibbase.org/img/filetypes/link.svg "link")
Paper doi bibtex @inproceedings{thakur_benchmarking_2023,
address = {Antwerp, Belgium},
title = {Benchmarking {Large} {Language} {Models} for {Automated} {Verilog} {RTL} {Code} {Generation}},
copyright = {https://doi.org/10.15223/policy-029},
url = {https://ieeexplore.ieee.org/document/10137086/},
doi = {10.23919/DATE56975.2023.10137086},
urldate = {2025-05-28},
booktitle = {2023 {Design}, {Automation} \& {Test} in {Europe} {Conference} \& {Exhibition} ({DATE})},
publisher = {IEEE},
author = {Thakur, Shailja and Ahmad, Baleegh and Fan, Zhenxing and Pearce, Hammond and Tan, Benjamin and Karri, Ramesh and Dolan-Gavitt, Brendan and Garg, Siddharth},
month = apr,
year = {2023},
keywords = {\#broken, Benchmark testing, Codes, Digital systems, Functional analysis, GPT, Hardware, Jab/\#DATE, LLM, Syntactics, Transformers, Verilog},
pages = {1--6},
}
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