@inproceedings{tonnellier2016hardware,
  title={Hardware architecture for lowering the error floor of LTE turbo codes},
  author={Tonnellier, Thibaud and Leroux, Camille and Le Gal, Bertrand and Jego, Christophe and Gadat, Benjamin and Van Wambeke, Nicolas},
  booktitle={2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)},
  pages={107--112},
  year={2016},
  organization={IEEE},
  url_Link={https://ieeexplore.ieee.org/abstract/document/7853805}
}

{"_id":"9K7whjFvQSKjCY58s","bibbaseid":"tonnellier-leroux-legal-jego-gadat-vanwambeke-hardwarearchitectureforloweringtheerrorflooroflteturbocodes-2016","authorIDs":["E7aoTNq7CPEBZWyN9"],"author_short":["Tonnellier, T.","Leroux, C.","Le Gal, B.","Jego, C.","Gadat, B.","Van Wambeke, N."],"bibdata":{"bibtype":"inproceedings","type":"inproceedings","title":"Hardware architecture for lowering the error floor of LTE turbo codes","author":[{"propositions":[],"lastnames":["Tonnellier"],"firstnames":["Thibaud"],"suffixes":[]},{"propositions":[],"lastnames":["Leroux"],"firstnames":["Camille"],"suffixes":[]},{"propositions":[],"lastnames":["Le","Gal"],"firstnames":["Bertrand"],"suffixes":[]},{"propositions":[],"lastnames":["Jego"],"firstnames":["Christophe"],"suffixes":[]},{"propositions":[],"lastnames":["Gadat"],"firstnames":["Benjamin"],"suffixes":[]},{"propositions":[],"lastnames":["Van","Wambeke"],"firstnames":["Nicolas"],"suffixes":[]}],"booktitle":"2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)","pages":"107–112","year":"2016","organization":"IEEE","url_link":"https://ieeexplore.ieee.org/abstract/document/7853805","bibtex":"@inproceedings{tonnellier2016hardware,\n title={Hardware architecture for lowering the error floor of LTE turbo codes},\n author={Tonnellier, Thibaud and Leroux, Camille and Le Gal, Bertrand and Jego, Christophe and Gadat, Benjamin and Van Wambeke, Nicolas},\n booktitle={2016 Conference on Design and Architectures for Signal and Image Processing (DASIP)},\n pages={107--112},\n year={2016},\n organization={IEEE},\n url_Link={https://ieeexplore.ieee.org/abstract/document/7853805}\n}\n\n\n","author_short":["Tonnellier, T.","Leroux, C.","Le Gal, B.","Jego, C.","Gadat, B.","Van Wambeke, N."],"key":"tonnellier2016hardware","id":"tonnellier2016hardware","bibbaseid":"tonnellier-leroux-legal-jego-gadat-vanwambeke-hardwarearchitectureforloweringtheerrorflooroflteturbocodes-2016","role":"author","urls":{" link":"https://ieeexplore.ieee.org/abstract/document/7853805"},"metadata":{"authorlinks":{"tonnellier, t":"https://ttonnellier.github.io/"}},"downloads":0,"html":""},"bibtype":"inproceedings","biburl":"ttonnellier.github.io/media/thibaud_no_dup.bib","creationDate":"2020-10-27T23:05:46.285Z","downloads":0,"keywords":[],"search_terms":["hardware","architecture","lowering","error","floor","lte","turbo","codes","tonnellier","leroux","le gal","jego","gadat","van wambeke"],"title":"Hardware architecture for lowering the error floor of LTE turbo codes","year":2016,"dataSources":["GqmNDkDGydyHL4Wvy","gGWoxvPgdGdw3LYAn"]}