A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic. Truesdell, D. S., Breiholz, J., Kamineni, S., Liu, N., Magyar, A., & Calhoun, B. H. IEEE solid-state circuits letters, 2019.
A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic [link]Paper  bibtex   
@article{594,
  author = {Daniel S. Truesdell and Jacob Breiholz and Sumanth Kamineni and Ningxi Liu and Albert Magyar and Benton H. Calhoun},
  title = {A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic},
  year = {2019},
  journal = {IEEE solid-state circuits letters},
  url = {https://doi.org/10.1109/lssc.2019.2938897}
}

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