A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability. Truesdell, D. S., Dissanayake, A., & Calhoun, B. H. IEEE solid-state circuits letters, 2019.
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Paper bibtex
Paper bibtex @article{608,
author = {Daniel S. Truesdell and Anjana Dissanayake and Benton H. Calhoun},
title = {A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability},
year = {2019},
journal = {IEEE solid-state circuits letters},
url = {https://doi.org/10.1109/lssc.2019.2946767}
}Downloads: 0
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