Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities. Valencia, F., Polian, I., & Regazzoni, F. In Leporati, F., Vitabile, S., & Skavhaug, A., editors, 24th Euromicro Conference on Digital System Design, DSD 2021, Palermo, Spain, September 1-3, 2021, pages 385–388, 2021. IEEE.
Extending Circuit Design Flow for Early Assessment of Fault Attack Vulnerabilities [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/dsd/ValenciaPR21,
  author    = {Felipe Valencia and
               Ilia Polian and
               Francesco Regazzoni},
  editor    = {Francesco Leporati and
               Salvatore Vitabile and
               Amund Skavhaug},
  title     = {Extending Circuit Design Flow for Early Assessment of Fault Attack
               Vulnerabilities},
  booktitle = {24th Euromicro Conference on Digital System Design, {DSD} 2021, Palermo,
               Spain, September 1-3, 2021},
  pages     = {385--388},
  publisher = {{IEEE}},
  year      = {2021},
  url       = {https://doi.org/10.1109/DSD53832.2021.00065},
  doi       = {10.1109/DSD53832.2021.00065},
  timestamp = {Fri, 15 Oct 2021 14:43:22 +0200},
  biburl    = {https://dblp.org/rec/conf/dsd/ValenciaPR21.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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