@article{DBLP:journals/tc/VenkatesanKSARR16,
  author    = {Rangharajan Venkatesan and
               Vivek Joy Kozhikkottu and
               Mrigank Sharad and
               Charles Augustine and
               Arijit Raychowdhury and
               Kaushik Roy and
               Anand Raghunathan},
  title     = {Cache Design with Domain Wall Memory},
  journal   = {{IEEE} Trans. Computers},
  volume    = {65},
  number    = {4},
  pages     = {1010--1024},
  year      = {2016},
  url       = {https://doi.org/10.1109/TC.2015.2506581},
  doi       = {10.1109/TC.2015.2506581},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tc/VenkatesanKSARR16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

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