Design and Implementation of a Decimation Filter for Hearing Aid Applications. Venugopalan, V., Abed, K., & Nerurkar, S. In Proceedings of IEEE SoutheastCon, pages 111–115, April, 2005. abstract bibtex In this paper we deal with the design and implementation of a decimation filter used for hearing aid applications. We implement the decimation filter using the canonic signed digit (CSD) representation. Each digital filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR architecture, the designed decimation filter architecture contributes to a hardware saving of 69%; in addition, it reduces the power dissipation by 83%, respectively.
@inproceedings{Venugopal2005Design-and,
abstract = {In this paper we deal with the design and implementation of a decimation filter used for hearing aid applications. We implement the decimation filter using the canonic signed digit (CSD) representation. Each digital filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. Compared to the comb-FIR-FIR architecture, the designed decimation filter architecture contributes to a hardware saving of 69{\%}; in addition, it reduces the power dissipation by 83{\%}, respectively.},
author = {Venugopalan, Vivek and Abed, Khalid and Nerurkar, Shailesh},
booktitle = {Proceedings of IEEE SoutheastCon},
date-added = {2020-01-15 12:00:21 -0500},
date-modified = {2020-01-15 12:00:21 -0500},
keywords = {digital filters; digital signal processing chips; field programmable gate arrays; hearing aids; power consumption; signal representation; DSP Blockset; Matlab; Simulink; Virtex-2 technology; Xilinx FPGA; canonic signed digit representation; decimation filter; digital filter simulation; hardware efficient architecture; hearing aid applications; power consumption},
pages = {111--115},
title = {Design and Implementation of a Decimation Filter for Hearing Aid Applications},
ty = {CONF},
year = {2005},
month = apr,
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We implement the decimation filter using the canonic signed digit (CSD) representation. Each digital filter structure is simulated using Matlab, and its complete architecture is captured using DSP Blockset and Simulink. The filter has been implemented on Xilinx FPGA using Virtex-2 technology. The resulting architecture is hardware efficient and consumes less power compared to conventional decimation filters. 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