High Throughput Implementations of Cryptography Algorithms on GPU and FPGA. Venugopalan, V. & Shila, D. In IEEE International Instrumentation and Measurement Technology Conference (I2MTC), pages 723-727, May, 2013. abstract bibtex Cryptography algorithms are ranked by their speed in encrypting/decrypting data and their robustness to withstand attacks. Real-time processing of data encryption/decryption is essential in network based applications to keep pace with the input data inhalation rate. The encryption/decryption steps are computationally intensive and exhibit high degree of parallelism. Field programmable gate arrays (FPGA) and graphics processing units (GPU) are being employed as cryptographic coprocessors to target different cryptography algorithms. In this paper, we target different encryption algorithms (TEA and XTEA) on GPU and FPGA platforms. We investigate the performance of the algorithms in terms of latency, throughput, gate equivalence, cost and ease of mapping on both platforms. We employ optimization techniques to realize high throughput in our custom configured implementations for coarse-grained parallel architectures. We propose a tool called Cryptographic Hardware Acceleration and Analysis Tool (CHAAT) that selects an optimal algorithm depending on the user's constraints with respect to hardware utilization, cost and security.
@inproceedings{Venugopal2013High-throu,
abstract = {Cryptography algorithms are ranked by their speed in encrypting/decrypting data and their robustness to withstand attacks. Real-time processing of data encryption/decryption is essential in network based applications to keep pace with the input data inhalation rate. The encryption/decryption steps are computationally intensive and exhibit high degree of parallelism. Field programmable gate arrays (FPGA) and graphics processing units (GPU) are being employed as cryptographic coprocessors to target different cryptography algorithms. In this paper, we target different encryption algorithms (TEA and XTEA) on GPU and FPGA platforms. We investigate the performance of the algorithms in terms of latency, throughput, gate equivalence, cost and ease of mapping on both platforms. We employ optimization techniques to realize high throughput in our custom configured implementations for coarse-grained parallel architectures. We propose a tool called Cryptographic Hardware Acceleration and Analysis Tool (CHAAT) that selects an optimal algorithm depending on the user's constraints with respect to hardware utilization, cost and security.},
author = {Venugopalan, Vivek and Shila, Devu},
booktitle = {IEEE International Instrumentation and Measurement Technology Conference (I2MTC)},
date-added = {2020-01-15 12:02:05 -0500},
date-modified = {2020-01-15 12:02:05 -0500},
issn = {1091-5281},
keywords = {Encryption;Field programmable gate arrays;Graphics processing units;Hardware;Logic gates;Throughput;Tiny Encryption Algorithm;cryptography;field programmable gate arrays;graphics processing units;parallel processing},
month = may,
pages = {723-727},
title = {{High Throughput Implementations of Cryptography Algorithms on GPU and FPGA}},
year = {2013},
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