Thermal aware test scheduling for stacked multi-chip-modules. Vinay, N. S., Rawat, I., Larsson, E., Gaur, M. S., & Singh, V. In 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010, pages 343–349, 2010.
Thermal aware test scheduling for stacked multi-chip-modules [link]Paper  doi  bibtex   
@inproceedings{DBLP:conf/ewdts/VinayRLGS10,
  author       = {N. S. Vinay and
                  Indira Rawat and
                  Erik Larsson and
                  Manoj Singh Gaur and
                  Virendra Singh},
  title        = {Thermal aware test scheduling for stacked multi-chip-modules},
  booktitle    = {2010 East-West Design {\&} Test Symposium, {EWDTS} 2010, St. Petersburg,
                  Russia, September 17-20, 2010},
  pages        = {343--349},
  year         = {2010},
  crossref     = {DBLP:conf/ewdts/2010},
  url          = {https://doi.org/10.1109/EWDTS.2010.5742053},
  doi          = {10.1109/EWDTS.2010.5742053},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ewdts/VinayRLGS10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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